The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for saving power by powering down an instruction fetch array based on a capacity history of the instruction buffer.
In a processor architecture, the instruction fetch unit is responsible for fetching instructions from an instruction cache for execution by execution units of the processor. The instruction fetch unit includes an instruction buffer which stores the fetched instructions before they can be sent to an instruction decode unit for subsequent decoding, scheduling, and execution. The instruction buffer is a critical resource in the processor architecture in that when the instruction buffer becomes full, instruction fetching is stalled.
In some processor architectures, when such a stall occurs, the instruction fetch unit's arrays are still powered up but there is no additional useful work being obtained from these arrays since instruction fetching is stalled awaiting a drain of instructions from the instruction buffer. Unfortunately, with known processor architectures, there is no ability to know early enough in the fetch sequence whether there will be room in the instruction buffer or not when the instructions arrive at the instruction buffer. This may lead to a bubble in the dispatch pipeline due to the processor not accessing the instruction fetch unit arrays because there was no room in the instruction buffer, but there actually being room in the instruction buffer when the instructions were available from the instruction fetch unit arrays. This causes a significant performance loss.
As a result, known processor architectures simply always keep the instruction fetch unit arrays powered up almost all of the time that the processor is operating. The only times where the instruction fetch unit arrays may be powered down is when there is an instruction cache miss or an effective to real address table (erat) miss pending.